In order to improve the response speed of a constant-voltage power supply circuit in response to the fluctuation of its output voltage, there is a known method of increasing a bias current supplied to a circuitry such as an error amplifying circuit constituting the constant-voltage power supply circuit. Another known method provides a second feedback loop capable of high-speed response in addition to the main feedback loop, and controls the output voltage by use of these two feedback loops.
In the method of increasing the bias current to the error amplifying circuit, only a limited increase in the bias current can be made since such an increase results in the current consumption of the constant-voltage power supply circuit being increased. In consideration of this, a certain circuit (see Japanese Patent Application Publication No. 3-158912) supplies the error amplifying circuit with a bias current proportional to the output current of the constant-voltage power supply circuit, thereby achieving both high-speed response and low current consumption.
FIG. 7 is a drawing showing an example of a constant-voltage power supply circuit which achieves such high-speed response and low power consumption, and is provided with an overcurrent protection circuit having a fold-back characteristic.
A constant-voltage power supply circuit 100 of FIG. 7 includes a reference voltage generating circuit 102 for generating and outputting a predetermined reference voltage Vref, an output-voltage-detection-purpose resistor R101 and output-voltage-detection-purpose resistor R102 for generating and outputting a divided voltage VFB by dividing the output voltage Vout that is the voltage appearing at the output terminal OUT, an output transistor M101 comprised of a PMOS transistor for controlling a current io produced at the output terminal OUT in response to the signal applied to the gate thereof, an error amplifying circuit 103 for controlling the operation of the output transistor M101 such as to make the divided voltage VFB equal to the reference voltage Vref, a bias current adjusting circuit 104 for adjusting the bias current of the error amplifying circuit 103 in response to the output current io, and an overcurrent protection circuit 105 having a fold-back output-voltage-versus-output-current characteristic that reduces the output current while lowering the output voltage Vout once the output current io exceeds a predetermined value.
The error amplifying circuit 103 amplifies a difference between the reference voltage Vref and the divided voltage VFB for provision to the gate of the output transistor M101, thereby controlling the operation of the output transistor M101 to set the output voltage Vout equal to a constant voltage.
In the bias current adjusting circuit 104, the drain current of a PMOS transistor M105 that serves to detect the output current io and outputs a current proportional to the output current io of the output transistor M101 increases as the output current io increases. The drain current of the PMOS transistor M105 is the drain current of an NMOS transistor M106, so that the drain currents of NMOS transistors M107 and M108 forming a current mirror circuit with the NMOS transistor M106 also increase.
The drain current of the NMOS transistor M107 is the bias current applied to an operational amplifier A101 of the error amplifying circuit 103, so that the bias current applied to the operational amplifier A101 increases in proportion to an increase in the output current io. The drain current of the NMOS transistor M108 is the bias current applied to a PMOS transistor M102, so that the bias current applied to the PMOS transistor M102 increases in proportion to an increase in the output current io. As a result, the response speed of the error amplifying circuit 103 responsive to the voltage fluctuation of the output voltage Vout increases as the output current io increases.
In the overcurrent protection circuit 105, when the output current io becomes a predetermined protection current amount, a voltage drop across a resistor R104 connecting between the drain of the PMOS transistor M103 and the ground potential exceeds the divided voltage VFB. As a result, the output voltage of an operational amplifier circuit A102 drops to turn on a PMOS transistor M104 to make it conductive, thereby suppressing the drop of the gate voltage of the output transistor M101. As shown in FIG. 8, consequently, the output voltage Vout is lowered, and the output current is reduced, resulting in the output current decreasing to become equal to the short-circuit current shown as “A” when the output voltage Vout is short-circuited, thereby protecting the constant-voltage power supply circuit 100 and a load 110 from an overcurrent. Such overcurrent protection circuit 105 is a so-called overcurrent protection circuit having a fold-back characteristic.
Since the output current io is an extremely large current when the overcurrent protection circuit 105 is operating, the bias current of the operational amplifier circuit A101 of the error amplifying circuit 103 is also large in such a case. The drive power of the output node of the operational amplifier A101 is thus extremely large, so that the drive power of the PMOS transistor M104 used in the overcurrent protection circuit 105 is not sufficient to bring the short-circuit current corresponding to the short-circuiting of the output voltage Vout to the point A shown in FIG. 8, resulting in the actual characteristics being those as shown by the solid line, which can bring the short-circuit current only to a point B. As a result, the power loss at the output transistor M101 becomes significant to generate excess heat, which may cause a failure to the IC when the constant-voltage power supply circuit is implemented as an IC chip.
In order to make the overcurrent protection circuit 105 operate fully to bring down the short-circuit current to the point A shown in FIG. 8, the drive power of the PMOS transistor M104 needs to be set far larger than the drive power of the error amplifying circuit 103.
An increase in the drive power of the PMOS transistor M104 requires an increase in the device size of the PMOS transistor M104, which results in the cost being increased due to an increase in the chip size when the constant-voltage power supply circuit 100 is implemented as an IC chip. Further, there is a need to increase the operating current of the overcurrent protection circuit 105, resulting in an increase in power consumption.
Accordingly, there is a need for a constant-voltage power supply circuit having an overcurrent protection circuit with a fold-back characteristic and a method of controlling such a constant-voltage power supply circuit in which the short-circuit current can be lowered to a predetermined current amount without increasing the device size of the PMOS transistor M104 and without increasing the operating current of the overcurrent protection circuit 105.